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US07936047B2 Method for realizing a contact of an integrated well in a semiconductor substrate, in particular for a base terminal of a bipolar transistor, with enhancement of the transistor performances 有权
用于实现半导体衬底中的集成阱的接触的方法，特别是用于双极晶体管的基极，与晶体管性能的增强

  • Patent Title: Method for realizing a contact of an integrated well in a semiconductor substrate, in particular for a base terminal of a bipolar transistor, with enhancement of the transistor performances
  • Patent Title (中): 用于实现半导体衬底中的集成阱的接触的方法，特别是用于双极晶体管的基极，与晶体管性能的增强
  • Application No.: US12039610
    Application Date: 2008-02-28
  • Publication No.: US07936047B2
    Publication Date: 2011-05-03
  • Inventor: Vincenzo Enea , Cesare Ronsisvalle
  • Applicant: Vincenzo Enea , Cesare Ronsisvalle
  • Applicant Address: IT Agrate Brianza
  • Assignee: STMicroelectronics S.r.l.
  • Current Assignee: STMicroelectronics S.r.l.
  • Current Assignee Address: IT Agrate Brianza
  • Agency: Seed IP Law Group PLLC
  • Agent Lisa K. Jorgenson; Robert Iannucci
  • Priority: ITMI2007A0405 20070301
  • Main IPC: H01L29/73
  • IPC: H01L29/73
Method for realizing a contact of an integrated well in a semiconductor substrate, in particular for a base terminal of a bipolar transistor, with enhancement of the transistor performances
Abstract:
A method realizes a contact of a first well of a first type of dopant integrated in a semiconductor substrate next to a second well of a second type of dopant and forming with it a parasitic diode. The method comprises: formation of the first well; formation of the second well next to the first well; definition of an oxide layer above the first and second wells; and formation of an electric contact layer above the oxide layer in correspondence with the first well for realizing an electric contact with it. The definition step of the oxide layer further comprises a deposition step of this oxide layer above the whole first well and a removal step of at least one portion of the oxide layer in correspondence with a contact area of the first well so that the contact area has a shorter length than a length of the first well.
Abstract(Chinese):

一种方法实现了集成在半导体衬底中的第一类掺杂剂的第一阱与第二类掺杂剂的第二阱相邻并与其形成寄生二极管的接触。 该方法包括：形成第一井; 在第一井旁边形成第二井; 在第一和第二阱上方的氧化物层的定义; 以及与第一阱对应地形成在氧化物层上方的电接触层，以实现与其的电接触。 氧化物层的定义步骤还包括在整个第一阱上方的该氧化物层的沉积步骤和与第一阱的接触面积对应的氧化物层的至少一部分的去除步骤，使得接触区域具有 比第一井的长度短的长度。

Public/Granted literature
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IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L29/00 专门适用于整流、放大、振荡或切换，并具有至少一个电位跃变势垒或表面势垒的半导体器件；具有至少一个电位跃变势垒或表面势垒，例如PN结耗尽层或载流子集结层的电容器或电阻器；半导体本体或其电极的零部件（H01L31/00至H01L47/00，H01L51/05优先；除半导体或其电极之外的零部件入H01L23/00；由在一个共用衬底内或其上形成的多个固态组件组成的器件入H01L27/00）
H01L29/66 .按半导体器件的类型区分的
H01L29/68 ..只能通过对一个不通有待整流、放大或切换的电流的电极供给电流或施加电位方可进行控制的（H01L29/96优先）
H01L29/70 ...双极器件
H01L29/72 ....晶体管型器件，如连续响应于所施加的控制信号的
H01L29/73 .....双极结型晶体管
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