Invention Grant
- Patent Title: Stacked package and method for forming stacked package
- Patent Title (中): 堆叠封装和堆叠封装形成方法
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Application No.: US12528739Application Date: 2007-05-14
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Publication No.: US07936058B2Publication Date: 2011-05-03
- Inventor: Masashi Hasegawa
- Applicant: Masashi Hasegawa
- Applicant Address: JP
- Assignee: Kabushiki Kaisha Nihon Micronics
- Current Assignee: Kabushiki Kaisha Nihon Micronics
- Current Assignee Address: JP
- Agency: Bacon & Thomas, PLLC
- International Application: PCT/JP2007/059863 WO 20070514
- International Announcement: WO2008/139605 WO 20081120
- Main IPC: H01L23/02
- IPC: H01L23/02
Abstract:
The present invention provides an inexpensive semiconductor chip module enabling sufficient heat dissipation without complicating the manufacture process.A semiconductor chip module according to the present invention includes a plurality of semiconductor chips to be stacked provided at the side face with a connection terminal to be coupled with a circuit pattern formed on the front face, interlayer wiring mutually connecting the connection terminals on the side faces of the respective semiconductor chips by a wiring pattern, and a formation space contributing to heat dissipation, formed between at least some layers of the semiconductor chips, to secure a formation face of the interlayer wiring.
Public/Granted literature
- US20100013072A1 STACKED PACKAGE AND METHOD FOR FORMING STACKED PACKAGE Public/Granted day:2010-01-21
Information query
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