Invention Grant
- Patent Title: Semiconductor device having a specified terminal layout pattern
- Patent Title (中): 具有指定的端子布局图案的半导体器件
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Application No.: US11945498Application Date: 2007-11-27
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Publication No.: US07936071B2Publication Date: 2011-05-03
- Inventor: Masaaki Abe , Kazuhiro Kijima
- Applicant: Masaaki Abe , Kazuhiro Kijima
- Applicant Address: JP
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: JP2004-163010 20040601
- Main IPC: H01L29/41
- IPC: H01L29/41

Abstract:
A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.
Public/Granted literature
- US20080088024A1 SEMICONDUCTOR DEVICE Public/Granted day:2008-04-17
Information query
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