Invention Grant
- Patent Title: Semiconductor device having dual damascene structure
- Patent Title (中): 具有双镶嵌结构的半导体器件
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Application No.: US12289905Application Date: 2008-11-06
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Publication No.: US07936072B2Publication Date: 2011-05-03
- Inventor: Toshiyuki Takewaki
- Applicant: Toshiyuki Takewaki
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: RENESAS Electronics Corporation
- Current Assignee: RENESAS Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: MGinn IP Law Group, PLLC
- Priority: JP2007-292708 20071112
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52

Abstract:
The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L
Public/Granted literature
- US20090121360A1 Semiconductor device having dual damascene structure Public/Granted day:2009-05-14
Information query
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