A start-up reset circuit includes a flip-flop and a clock signal generator. The clock signal generator generates a first clock signal and a second clock signal, wherein there is a phase difference between the first clock signal and the second clock signal. The flip-flop receives an operation voltage and has a setup time, and further includes an input terminal to receive the first clock signal, a clock input terminal to receive the second clock signal, and an output terminal to output a reset signal, wherein the setup time corresponds to the operation voltage.