A frequency synthesis phase-locked loop architecture using a regenerative sampling latch is described. The frequency divider typically employed in the feedback path of a frequency synthesis phase-locked loop is replaced by a regenerative sampling latch with a binary output. The regenerative sampling latch subsamples the frequency synthesizer output to produce a low-frequency aliased signal that can be processed further or directly used to lock the phase-locked loop. This architecture is referred to as an alias-locked loop. The relaxed constraints on the regenerative sampling latch make it possible to create high-speed frequency synthesizer phase-locked loops without the suffering the limitations imposed by traditional dividers connected directly to the oscillator output.