Invention Grant
- Patent Title: Dual-reference delay-locked loop (DLL)
- Patent Title (中): 双参考延迟锁定环(DLL)
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Application No.: US11241550Application Date: 2005-09-30
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Publication No.: US07936194B2Publication Date: 2011-05-03
- Inventor: Jed D. Griffin
- Applicant: Jed D. Griffin
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
Embodiments of the present invention are directed to a dual-reference delay-locked loop that includes a first delay element that delays a clock signal. The rising phase and the falling phase of the delayed clock signal are used as a first and a second reference phases, respectively, for a phase detector. A second delay element delays the first reference signal with a tracking phase that centers between the two reference phases. The phase detector detects a difference between the average of the reference phases and the tracking or resultant phase and outputs a difference signal that biases the delay elements to slew to the left or the right so that the resultant phase is centered between the reference phases corresponding to the rising and falling edges of the incoming clock.
Public/Granted literature
- US20070076831A1 Dual-reference delay-locked loop (DLL) Public/Granted day:2007-04-05
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