A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal.