Invention Grant
US07936198B2 Progamable control clock circuit for arrays 有权
阵列控制时钟电路

Progamable control clock circuit for arrays
Abstract:
A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.
Public/Granted literature
Information query
Patent Agency Ranking
0/0