Invention Grant
- Patent Title: Bias circuit for a MOS device
- Patent Title (中): 用于MOS器件的偏置电路
-
Application No.: US12184148Application Date: 2008-07-31
-
Publication No.: US07936208B2Publication Date: 2011-05-03
- Inventor: Steven Mark Clements , Hayden C. Cranford, Jr. , Amar Chandra Mahadeo Dwarka , John Farley Ewen
- Applicant: Steven Mark Clements , Hayden C. Cranford, Jr. , Amar Chandra Mahadeo Dwarka , John Farley Ewen
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yee & Associates, P.C.
- Agent Ian D. MacKinnon
- Main IPC: G05F3/02
- IPC: G05F3/02
Abstract:
A method and circuit for providing a bias voltage to a MOS device is disclosed. The method and circuit comprise utilizing at least one diode connected circuit to provide a voltage that tracks process, voltage and temperature variations of a semiconductor device. The method and circuit includes utilizing a current mirror circuit coupled to the at least one diode connected circuit to generate a bias voltage for the body of the semiconductor device from the voltage. The bias voltage allows for compensation for the process, voltage and temperature variations.
Public/Granted literature
- US20100026376A1 BIAS CIRCUIT FOR A MOS DEVICE Public/Granted day:2010-02-04
Information query
IPC分类:
