In a display control circuit for controlling a display of a display device, data which is stored in a memory is inputted to a FIFO circuit by a DMA controller, and the FIFO circuit transmits the stored data to the display device at a rising edge of an inputted clock PCLK. A clock mask circuit transmits the inputted clock PCLK to the display device as a display clock PCLK′ while the FIFO circuit is not underflow. On the other hand, the clock mask circuit masks the inputted clock PCLK while the FIFO circuit is underflow, and transmits the display clock PCLK′ whose level is kept high to the display device. As a result, a display position of display data does not shift even if underflow occurs in the FIFO circuit.