Invention Grant
- Patent Title: On-chip interconnect-stack cooling using sacrificial interconnect segments
- Patent Title (中): 使用牺牲互连段的片上互连堆栈冷却
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Application No.: US12158989Application Date: 2006-12-19
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Publication No.: US07936563B2Publication Date: 2011-05-03
- Inventor: Laurent Gosset , Vincent Arnal
- Applicant: Laurent Gosset , Vincent Arnal
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP05301103 20051223
- International Application: PCT/EP2006/069910 WO 20061219
- International Announcement: WO2007/071674 WO 20070628
- Main IPC: H05K7/20
- IPC: H05K7/20 ; H01L23/367 ; H01L21/764
Abstract:
The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.
Public/Granted literature
- US20080266787A1 On-Chip Interconnect-Stack Cooling Using Sacrificial Interconnect Segments Public/Granted day:2008-10-30
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