The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a second module (M2). The first module (M1) provides a first current limited to a maximum value (Iref+Ibias). The second module (M2) provides a second current which decreases from a value higher than the maximum value at the start of a sensing operation until a value lower than the maximum value at the end of the sensing operation. The memory circuit has a third module (CS2) for sinking a third current (Ibias) at a side of the switching device (T2) coupled to the memory element (T1).