Invention Grant
US07936624B2 Reduced power bitline precharge scheme for low power applications in memory devices
有权
用于存储器件中的低功率应用的减少功率位线预充电方案
- Patent Title: Reduced power bitline precharge scheme for low power applications in memory devices
- Patent Title (中): 用于存储器件中的低功率应用的减少功率位线预充电方案
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Application No.: US11965517Application Date: 2007-12-27
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Publication No.: US07936624B2Publication Date: 2011-05-03
- Inventor: Michael Patrick Clinton
- Applicant: Michael Patrick Clinton
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Dawn V. Stephens; Wade James Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A method and system are described for a two step precharging of bitlines in a memory array. In the first step a partial precharge of the bitline is accomplished with a lower power supply, the second step completes the bitline precharge with the higher power supply. Since the higher power supply must ultimately supply the final bitline precharge voltage achieving a partial bitline precharge with a lower power supply will result in lower sram and system power.
Public/Granted literature
- US20080181038A1 Reduced Power Bitline Precharge Scheme For Low Power Applications In Memory Devices Public/Granted day:2008-07-31
Information query
