Invention Grant
US07936630B1 Method and apparatus for calibrating a read/write channel in a memory arrangement
有权
用于校准存储器装置中的读/写通道的方法和装置
- Patent Title: Method and apparatus for calibrating a read/write channel in a memory arrangement
- Patent Title (中): 用于校准存储器装置中的读/写通道的方法和装置
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Application No.: US12689891Application Date: 2010-01-19
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Publication No.: US07936630B1Publication Date: 2011-05-03
- Inventor: Aditya Ramamoorthy , Gregory Burd , Xueshi Yang
- Applicant: Aditya Ramamoorthy , Gregory Burd , Xueshi Yang
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: G11C7/02
- IPC: G11C7/02

Abstract:
Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing data into and reading data from the memory cells. At least two memory cells are employed as reference cells to output a plurality of pilot signals. The memory apparatus also includes a channel block operatively coupled to the memory block, and adapted to facilitate the writing and reading of data into and from the memory cells. The channel block is also adapted to receive the pilot signals and determine one or more disturbance parameters based at least in part on the pilot signals and to compensate the read back signals based at least in part on the determined one or more disturbance parameters during said reading of data from the memory cells. Other embodiments may be described and claimed.
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