A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-multiplexer. The address decoder provides a plurality of column selection signals capable of being a boundary value. The first Y-multiplexer corresponds to the first memory block and provides a first boundary data channel for a boundary cell of the first memory block. The second Y-multiplexer corresponds to the second memory block and provides a second boundary data channel for a boundary cell of the second memory block. The first and the second boundary data channels are enabled simultaneously in response to the boundary value for outputting boundary data stored in the boundary cell of the first memory block and that of the second memory block.