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US07936809B2 Economical, scalable transceiver jitter test 有权
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Economical, scalable transceiver jitter test
Abstract:
Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.
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