Invention Grant
US07937252B2 CMOS model generating apparatus and method, program of the method and recording medium
失效
CMOS模型生成装置和方法,该方法和记录介质的程序
- Patent Title: CMOS model generating apparatus and method, program of the method and recording medium
- Patent Title (中): CMOS模型生成装置和方法,该方法和记录介质的程序
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Application No.: US12083949Application Date: 2006-10-23
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Publication No.: US07937252B2Publication Date: 2011-05-03
- Inventor: Hidetoshi Onodera , Xuliang Zhang , Nobuto Ono
- Applicant: Hidetoshi Onodera , Xuliang Zhang , Nobuto Ono
- Applicant Address: JP JP
- Assignee: Kyoto University,Jedat Innovation Inc.
- Current Assignee: Kyoto University,Jedat Innovation Inc.
- Current Assignee Address: JP JP
- Agent Gerald E. Hespos; Michael J. Porco
- Priority: JP2005-308700 20051024
- International Application: PCT/JP2006/321057 WO 20061023
- International Announcement: WO2007/049555 WO 20070503
- Main IPC: G06F7/60
- IPC: G06F7/60 ; G06F17/50 ; G06G7/62 ; H01L27/108 ; H01L27/118

Abstract:
A CMOS model generating apparatus 1 according to the present invention generates a CMOS model by converting an In-Ip space into an xn-xp space such that a typical condition TT and corner conditions FF, SS in the In-Ip space become (0, 0), (α, α) and (−α, −α) in the xn-xp space, determining an ellipse fitting to the respective mappings of the corner conditions FF, SS, FS and SF with the mapping (0, 0) of the typical condition TT as a center, expressing two independent principal components in the form of a Gaussian distribution using the major and minor axes of this ellipse as axes of the principal components, and obtaining a probability distribution determining deviations of the Gaussian distribution such that the cumulative probability within this ellipse becomes equal to the one presumed by the corner conditions FF, SS, FS and SF.
Public/Granted literature
- US20080262807A1 Cmos Model Generating Apparatus and Method, Program of the Method and Recording Medium Public/Granted day:2008-10-23
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