A data compression architecture comprises a shift register structure comprising first and second parallel paths, each comprising several shift register elements for storing previously received data characters. Each shift register element in the first path is paired with a respective shift register element in the second path. An input shift register stores input data characters in pairs during successive clock cycles. Logic circuitry compares the input data characters with each of the previously received data characters stored in the pairs of shift register elements to detect a match during one or more clock cycles. The logic circuitry determines a length of a sequence of received input data characters by determining a number of clock cycles during which a match is detected in a particular pair of shift register elements, and applies a correction factor based on a type of match detected at a beginning and end of the sequence.