Invention Grant
- Patent Title: Regularly occurring write back scheme for cache soft error reduction
- Patent Title (中): 定期发布回写方案缓存软错误减少
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Application No.: US11670381Application Date: 2007-02-01
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Publication No.: US07937531B2Publication Date: 2011-05-03
- Inventor: Somnath Mitra
- Applicant: Somnath Mitra
- Applicant Address: US CA San Jose
- Assignee: Cisco Technology, Inc.
- Current Assignee: Cisco Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Stolowitz Ford Cowger LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/16 ; G06F13/00
Abstract:
In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries are flushed.
Public/Granted literature
- US20080189489A1 REGULARLY OCCURRING WRITE BACK SCHEME FOR CACHE SOFT ERROR REDUCTION Public/Granted day:2008-08-07
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