Invention Grant
US07937561B2 Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture
有权
合并微指令以最大限度地减少乱序执行微处理器中可变数据大小宏建筑的源依赖
- Patent Title: Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture
- Patent Title (中): 合并微指令以最大限度地减少乱序执行微处理器中可变数据大小宏建筑的源依赖
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Application No.: US12062028Application Date: 2008-04-03
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Publication No.: US07937561B2Publication Date: 2011-05-03
- Inventor: Gerard M. Col , Terry Parks
- Applicant: Gerard M. Col , Terry Parks
- Applicant Address: TW Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW Taipei
- Agent E. Alan Davis; James W. Huffman
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register. Specifically, the execution unit directs the 8-bit result into the lower 8 bits of the N-bit result and directs the upper N-8 bits of the N-bit first source register into corresponding upper N-8 bits of the N-bit result.
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