A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.