Invention Grant
- Patent Title: Design-for-test-aware hierarchical design planning
- Patent Title (中): 设计为测试感知层次设计规划
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Application No.: US12123209Application Date: 2008-05-19
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Publication No.: US07937677B2Publication Date: 2011-05-03
- Inventor: Hung-Chun Chien , Ben Mathew , Padmashree Takkars , Bang Liu , Chang-Wei Tai , Xiao-Ming Xiong , Gary K. Yeap
- Applicant: Hung-Chun Chien , Ben Mathew , Padmashree Takkars , Bang Liu , Chang-Wei Tai , Xiao-Ming Xiong , Gary K. Yeap
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Bever, Hoffman & Harms, LLP
- Agent Jeanette S. Harms
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.
Public/Granted literature
- US20090288045A1 Design-For-Test-Aware Hierarchical Design Planning Public/Granted day:2009-11-19
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