Invention Grant
- Patent Title: Interposer and electronic device fabrication method
- Patent Title (中): 内插器和电子器件制造方法
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Application No.: US12213321Application Date: 2008-06-18
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Publication No.: US07937830B2Publication Date: 2011-05-10
- Inventor: Takeshi Shioga , Yoshikatsu Ishizuki , John David Baniecki , Kazuaki Kurihara
- Applicant: Takeshi Shioga , Yoshikatsu Ishizuki , John David Baniecki , Kazuaki Kurihara
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Kratz, Quintos & Hanson, LLP
- Priority: JP2005-287065 20050930
- Main IPC: H05K3/30
- IPC: H05K3/30 ; B29C65/00

Abstract:
An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.
Public/Granted literature
- US20080257487A1 Interposer and electronic device fabrication method Public/Granted day:2008-10-23
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