Invention Grant
- Patent Title: Method for fabricating integrated circuit structures
- Patent Title (中): 集成电路结构的制造方法
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Application No.: US12499622Application Date: 2009-07-08
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Publication No.: US07939421B2Publication Date: 2011-05-10
- Inventor: Chiang Hung Lin
- Applicant: Chiang Hung Lin
- Applicant Address: TW Kueishan
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan
- Agency: Hamre, Schumann, Mueller & Larson, P.C.
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/44

Abstract:
A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer. In another embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal nitride layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal and metal nitride layer.
Public/Granted literature
- US20110008961A1 METHOD FOR FABRICATING INTEGRATED CIRCUIT STRUCTURES Public/Granted day:2011-01-13
Information query
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