Invention Grant
US07939863B2 Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
有权
在线性双极CMOS工艺中,低噪声JFET和MOS的区域高效3D集成
- Patent Title: Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process
- Patent Title (中): 在线性双极CMOS工艺中,低噪声JFET和MOS的区域高效3D集成
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Application No.: US12537352Application Date: 2009-08-07
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Publication No.: US07939863B2Publication Date: 2011-05-10
- Inventor: Pinghai Hao , Marie Denison
- Applicant: Pinghai Hao , Marie Denison
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/78 ; H01L21/762

Abstract:
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.
Public/Granted literature
- US20100032728A1 AREA EFFICIENT 3D INTEGRATION OF LOW NOISE JFET AND MOS IN LINEAR BIPOLAR CMOS PROCESS Public/Granted day:2010-02-11
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