Invention Grant
US07939916B2 Wafer level CSP packaging concept 有权
晶圆级CSP包装概念

Wafer level CSP packaging concept
Abstract:
An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
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