Invention Grant
- Patent Title: Wafer level CSP packaging concept
- Patent Title (中): 晶圆级CSP包装概念
-
Application No.: US11627041Application Date: 2007-01-25
-
Publication No.: US07939916B2Publication Date: 2011-05-10
- Inventor: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
- Applicant: Alan O'Donnell , Oliver Kierse , Thomas M. Goida
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Sunstein Kann Murphy & Timbers LLP
- Main IPC: H01L23/552
- IPC: H01L23/552

Abstract:
An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
Public/Granted literature
- US20080179730A1 Wafer Level CSP Packaging Concept Public/Granted day:2008-07-31
Information query
IPC分类: