Invention Grant
- Patent Title: Low leakage and data retention circuitry
- Patent Title (中): 低泄漏和数据保持电路
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Application No.: US12542352Application Date: 2009-08-17
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Publication No.: US07940081B2Publication Date: 2011-05-10
- Inventor: Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
- Applicant: Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
- Applicant Address: CA Ottawa, Ontario
- Assignee: MOSAID Technologies Incorporated
- Current Assignee: MOSAID Technologies Incorporated
- Current Assignee Address: CA Ottawa, Ontario
- Agency: Hamilton, Brook, Smith & Reynolds, P.C.
- Main IPC: H03K19/173
- IPC: H03K19/173

Abstract:
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
Public/Granted literature
- US20100060319A1 LOW LEAKAGE AND DATA RETENTION CIRCUITRY Public/Granted day:2010-03-11
Information query
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