An integrated circuit including an array of memory cells, a circuit, volatile storage, and non-volatile storage. The circuit is configured to detect defective memory cells in the array of memory cells and provide addresses of the defective memory cells. The volatile storage is configured to store the addresses, where each entry in the volatile storage includes one of the addresses and a volatile storage master bit. The non-volatile storage is configured to store the addresses, where each entry in the non-volatile storage includes one of the addresses and a non-volatile storage master bit.