Invention Grant
- Patent Title: Muting circuit and semiconductor integrated circuit
- Patent Title (中): 静音电路和半导体集成电路
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Application No.: US11481158Application Date: 2006-07-05
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Publication No.: US07940940B2Publication Date: 2011-05-10
- Inventor: Yasunobu Kakumoto , Keiichi Fujii
- Applicant: Yasunobu Kakumoto , Keiichi Fujii
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Hamre, Schumann, Mueller & Larson, P.C.
- Priority: JP2005-200161 20050708
- Main IPC: H04B15/00
- IPC: H04B15/00 ; H03F1/14
Abstract:
A muting circuit of the present invention includes: an input terminal that receives a control signal for allowing switching between ON and OFF of a mute operation; and a muting transistor connected to the input terminal and an output terminal of the amplifier. The muting transistor is a MOS transistor, and a gate is connected to the input terminal, a drain is connected to the output terminal of the amplifier, and a source is grounded. Consequently, a shot noise due to a DC difference caused when a mute state is switched between ON and OFF can be suppressed.
Public/Granted literature
- US20070009110A1 Muting circuit and semiconductor integrated circuit Public/Granted day:2007-01-11
Information query
