Invention Grant
- Patent Title: Fault tolerant cell array architecture
- Patent Title (中): 容错单元阵列架构
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Application No.: US11933705Application Date: 2007-11-01
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Publication No.: US07941572B2Publication Date: 2011-05-10
- Inventor: Richard S. Norman
- Applicant: Richard S. Norman
- Agency: Ogilvy Renault, LLP
- Main IPC: G01S1/02
- IPC: G01S1/02

Abstract:
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
Public/Granted literature
- US20080059761A1 FAULT TOLERANT CELL ARRAY ARCHITECTURE Public/Granted day:2008-03-06
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