Invention Grant
US07941679B2 Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design
有权
用于计算功率节省并确定集成电路设计的优选时钟门控电路的方法
- Patent Title: Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design
- Patent Title (中): 用于计算功率节省并确定集成电路设计的优选时钟门控电路的方法
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Application No.: US11837174Application Date: 2007-08-10
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Publication No.: US07941679B2Publication Date: 2011-05-10
- Inventor: David L. Allen
- Applicant: David L. Allen
- Applicant Address: US CA San Jose
- Assignee: Atrenta, Inc.
- Current Assignee: Atrenta, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F1/00
- IPC: G06F1/00
Abstract:
A method for computing the power savings in an integrated circuit (IC) design is disclosed. The method computes the difference in power savings between techniques used for clock gating. Based on the computation results, the method outputs a script to control the implementation tool so as to provide for the best implementation clock gating technique in terms of power and area savings.
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