Invention Grant
- Patent Title: Scan test circuit and scan test control method
- Patent Title (中): 扫描测试电路和扫描测试控制方法
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Application No.: US12081929Application Date: 2008-04-23
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Publication No.: US07941720B2Publication Date: 2011-05-10
- Inventor: Kiyoshi Mikami
- Applicant: Kiyoshi Mikami
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group PLLC
- Priority: JP2007-120178 20070427
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/40

Abstract:
A scan test circuit in the present invention includes a control FF for inputting a control signal, and a scan path chain configured of scan storage elements to operate in a shift operation mode when an output of the control FF is a first status value, and in a normal operation mode when the output is a second status value. When the control signal is switched from the first status value to the second status value, the control FF outputs the second status value to multiple scan storage elements synchronously with a first clock pulse, after the switching, of a clock provided to multiple scan storage elements. When the scan control signal is switched from the second status value to the first status value, the control FF outputs the first status value to multiple scan storage elements at a timing of the control signal switching.
Public/Granted literature
- US20080270859A1 Scan test circuit and scan test control method Public/Granted day:2008-10-30
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