Invention Grant
- Patent Title: Method for functional verification of an integrated circuit model for constituting a verification platform, equipment emulator and verification platform
- Patent Title (中): 用于构建验证平台,设备仿真器和验证平台的集成电路模型的功能验证方法
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Application No.: US12133085Application Date: 2008-06-04
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Publication No.: US07941771B2Publication Date: 2011-05-10
- Inventor: Anne Kaszynski , Jacques Abily
- Applicant: Anne Kaszynski , Jacques Abily
- Applicant Address: FR Les Clayes Sous Bois
- Assignee: Bull S.A.
- Current Assignee: Bull S.A.
- Current Assignee Address: FR Les Clayes Sous Bois
- Agency: Miles & Stockbridge P.C.
- Priority: FR0209691 20020730
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45 ; G06F9/455

Abstract:
A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.
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