Invention Grant
- Patent Title: Pattern layout of integrated circuit
- Patent Title (中): 集成电路图案布局
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Application No.: US11943771Application Date: 2007-11-21
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Publication No.: US07941782B2Publication Date: 2011-05-10
- Inventor: Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
- Applicant: Yasunobu Kai , Kazuo Hatakeyama , Hidefumi Mukai , Hiromitsu Mashita , Koji Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2006-315560 20061122
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
In a pattern layout which includes a first device pattern having a uniformly repeated pattern group having first lines and first spaces formed parallel to one anther and uniformly arranged with constant width at a constant pitch and a non-uniformly repeated pattern group having first lines and first spaces non-uniformly arranged, and a second device pattern arranged adjacent to the end portion of the non-uniformly repeated pattern group in an arrangement direction thereof and having second lines and second spaces whose widths are larger than the widths of the first lines and first spaces of the non-uniformly repeated pattern group, at least part of the widths of the first lines and the first spaces of the non-uniformly repeated pattern group is made larger than the width of the first line or the width of the first space of the uniformly repeated pattern group.
Public/Granted literature
- US20080137421A1 PATTERN LAYOUT OF INTEGRATED CIRCUIT Public/Granted day:2008-06-12
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