Invention Grant
US07947530B2 Method of manufacturing wafer level package including coating and removing resin over the dicing lines
有权
制造晶片级封装的方法，包括在切割线上涂覆和除去树脂
- Patent Title: Method of manufacturing wafer level package including coating and removing resin over the dicing lines
- Patent Title (中): 制造晶片级封装的方法，包括在切割线上涂覆和除去树脂
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Application No.: US12453273Application Date: 2009-05-05
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Publication No.: US07947530B2Publication Date: 2011-05-24
- Inventor: Jin Gu Kim , Young Do Kweon , Hyung Jin Jeon , Seung Wook Park , Hee Kon Lee , Seon Hee Moon
- Applicant: Jin Gu Kim , Young Do Kweon , Hyung Jin Jeon , Seung Wook Park , Hee Kon Lee , Seon Hee Moon
- Applicant Address: KR Suwon
- Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee: Samsung Electro-Mechanics Co., Ltd.
- Current Assignee Address: KR Suwon
- Priority: KR10-2008-0130219 20081219
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50
Abstract:
The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.
Public/Granted literature
- US20100159646A1 Method of manufacturing wafer level package Public/Granted day:2010-06-24
Information query
IPC分类:
