A product-sum operation circuit has delay circuits of the first to the (n−1)th stage for delaying musical tone data, multiplying circuits 60-6(n−1) for multiplying the musical signal data or the delayed musical signal data output from the delay circuits by impulse response coefficients, and adders 71-7(n−1) for summing up data output from the multiplying circuits. The product-sum operation circuit is provided with a feed back circuit. The feed back circuit includes a multiplying circuit 80 that receives the delayed data from the delay circuit at the (n−1)th stage and multiplies the received data by a multiplication coefficient, and an adder 81 for adding data from the multiplying circuit 80 to the delayed data from the delay circuit at the “p”th stage.