Invention Grant
- Patent Title: Power MOS transistor device and layout
- Patent Title (中): 功率MOS晶体管器件和布局
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Application No.: US12122722Application Date: 2008-05-19
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Publication No.: US07948032B2Publication Date: 2011-05-24
- Inventor: Hsin-Ming Lee , Chih-Heng Chang
- Applicant: Hsin-Ming Lee , Chih-Heng Chang
- Applicant Address: TW Hsinchu
- Assignee: Novatek Microelectronics Corp.
- Current Assignee: Novatek Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW97103467A 20080130
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A power metal-oxide semiconductor (MOS) transistor device is provided. The power MOS transistor device includes a drain region disposed in a substrate, a gate structure layer disposed over the substrate, and enclosing a periphery of the drain region, and a source region formed in the substrate and distributed at an outer periphery of the gate structure layer. In addition, the MOS transistor device can, for example, form a transistor array.
Public/Granted literature
- US20090189220A1 POWER MOS TRANSISTOR DEVICE AND LAYOUT Public/Granted day:2009-07-30
Information query
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