Invention Grant
- Patent Title: Logic circuit
- Patent Title (中): 逻辑电路
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Application No.: US11661132Application Date: 2004-08-27
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Publication No.: US07948291B2Publication Date: 2011-05-24
- Inventor: Haruo Kawakami
- Applicant: Haruo Kawakami
- Applicant Address: JP Kawasaki
- Assignee: Fuji Electric Holdings Co., Ltd.
- Current Assignee: Fuji Electric Holdings Co., Ltd.
- Current Assignee Address: JP Kawasaki
- Agency: Rabin & Berdo, PC
- International Application: PCT/JP2004/012370 WO 20040827
- International Announcement: WO2006/022017 WO 20060302
- Main IPC: H03K3/02
- IPC: H03K3/02 ; H03K3/33 ; H03K3/00

Abstract:
The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.
Public/Granted literature
- US20080258136A1 Logic Circuit Public/Granted day:2008-10-23
Information query
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