Invention Grant
- Patent Title: Processor architecture with wide operand cache
- Patent Title (中): 具有宽操作数缓存的处理器架构
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Application No.: US11982051Application Date: 2007-10-31
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Publication No.: US07948496B2Publication Date: 2011-05-24
- Inventor: Craig Hansen , John Moussouris , Alexia Massalin
- Applicant: Craig Hansen , John Moussouris , Alexia Massalin
- Applicant Address: US CA Santa Clara
- Assignee: MicroUnity Systems Engineering, Inc.
- Current Assignee: MicroUnity Systems Engineering, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: JP11-057259 19990304
- Main IPC: G06T1/00
- IPC: G06T1/00 ; G06T15/00 ; G06F15/00

Abstract:
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
Public/Granted literature
- US20090100227A1 Processor architecture with wide operand cache Public/Granted day:2009-04-16
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