Invention Grant
- Patent Title: Transparent level 2 cache controller
- Patent Title (中): 透明级2缓存控制器
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Application No.: US12728583Application Date: 2010-03-22
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Publication No.: US07949833B1Publication Date: 2011-05-24
- Inventor: Hong-Yi Chen , Geoffrey K. Yung
- Applicant: Hong-Yi Chen , Geoffrey K. Yung
- Applicant Address: BM Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BM Hamilton
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
Information query
