Invention Grant
US07949883B2 Cryptographic CPU architecture with random instruction masking to thwart differential power analysis
有权
具有随机指令掩码的加密CPU架构，以阻止差分功率分析
- Patent Title: Cryptographic CPU architecture with random instruction masking to thwart differential power analysis
- Patent Title (中): 具有随机指令掩码的加密CPU架构，以阻止差分功率分析
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Application No.: US10864568Application Date: 2004-06-08
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Publication No.: US07949883B2Publication Date: 2011-05-24
- Inventor: David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
- Applicant: David B. Shu , Lap-Wai Chow , William M. Clark, Jr.
- Applicant Address: US CA Malibu
- Assignee: HRL Laboratories, LLC
- Current Assignee: HRL Laboratories, LLC
- Current Assignee Address: US CA Malibu
- Agency: Ladas & Parry
- Main IPC: G06F11/30
- IPC: G06F11/30 ; G06F12/14
Abstract:
An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
Public/Granted literature
- US20050273631A1 Cryptographic CPU architecture with random instruction masking to thwart differential power analysis Public/Granted day:2005-12-08
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