Invention Grant
US07949982B2 Semiconductor integrated circuit design system, semiconductor integrated circuit design method, and computer readable medium
有权
半导体集成电路设计系统,半导体集成电路设计方法和计算机可读介质
- Patent Title: Semiconductor integrated circuit design system, semiconductor integrated circuit design method, and computer readable medium
- Patent Title (中): 半导体集成电路设计系统,半导体集成电路设计方法和计算机可读介质
-
Application No.: US12331791Application Date: 2008-12-10
-
Publication No.: US07949982B2Publication Date: 2011-05-24
- Inventor: Toshiaki Ueda
- Applicant: Toshiaki Ueda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Sprinkle IP Law Group
- Priority: JP2007-327437 20071219
- Main IPC: G06F9/455
- IPC: G06F9/455

Abstract:
A semiconductor integrated circuit design method has extracting connection-permitted patterns which are permitted to connect to each other in a layout pattern, disconnection-permitted patterns which exercise no effect on a circuit operation even when disconnected in the layout pattern, and a multicut via which suffices when connection is made to at least one via thereof in the layout pattern, by using a net list and a cell library; conducting LRC (Lithography Rule Check) processing on the layout pattern to which a correction pattern resulting from OPC (Optical Proximity Correction) processing is added, and detecting an error part; and judging the error part either as a false error when the error part is included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, or as a true error when the error part is not included in the connection-permitted patterns, the disconnection-permitted patterns, or the multicut via extracted, and making a pattern correction to the error part when the error part is judged as the true error.
Public/Granted literature
Information query