A source electrode and a drain electrode on a silicon oxide film (31) each has a double-layered structure of an ITO film (32), a transparent electrode, and a metal film (33) formed on the ITO film (32). A gap (35), no source electrode and drain electrode region, is formed between the source electrode and the drain electrode. A silicon nitride film (34) (a gate insulating film) is formed on the source electrode and the drain electrode and in the gap (35). The silicon nitride film (34) is a first region D1 having a relatively large thickness and a second region D2 having a relatively small thickness. The region D2 of the silicon nitride film (34) is provided with an MIM structure. A gate bus layer (36) is formed on the silicon nitride film (34). An MIM structure is formed in the second region D2.