Wafer level chip scale package and process of manufacture

Invention Grant

US07955893B2 Wafer level chip scale package and process of manufacture 有权

Title translation: 晶圆级芯片级封装及制造工艺

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Patent Title: Wafer level chip scale package and process of manufacture
Patent Title (中): 晶圆级芯片级封装及制造工艺
Application No.: US12023921

Application Date: 2008-01-31
Publication No.: US07955893B2

Publication Date: 2011-06-07
Inventor: Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
Applicant: Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
Applicant Address: BM Hamilton
Assignee: Alpha & Omega Semiconductor, Ltd
Current Assignee: Alpha & Omega Semiconductor, Ltd
Current Assignee Address: BM Hamilton
Agency: JDI Patent
Agent Joshua D. Isenberg
Main IPC: H01L21/00
IPC: H01L21/00

Wafer level chip scale package and process of manufacture

Abstract:

Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

Abstract(Chinese):

封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

Public/Granted literature

US20090194880A1 WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE Public/Granted day:2009-08-06

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备