Invention Grant
US07955897B2 Chip structure and stacked chip package as well as method for manufacturing chip structures
有权
芯片结构和堆叠芯片封装以及芯片结构的制造方法
- Patent Title: Chip structure and stacked chip package as well as method for manufacturing chip structures
- Patent Title (中): 芯片结构和堆叠芯片封装以及芯片结构的制造方法
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Application No.: US12188621Application Date: 2008-08-08
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Publication No.: US07955897B2Publication Date: 2011-06-07
- Inventor: Tsung Yueh Tsai , Yi Shao Lai , Cheng Wei Huang
- Applicant: Tsung Yueh Tsai , Yi Shao Lai , Cheng Wei Huang
- Applicant Address: TW Pingtung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Pingtung
- Agency: Lowe, Hauptman, Ham & Berner, LLP
- Priority: TW97108439A 20080311
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals.
Public/Granted literature
- US20090230564A1 CHIP STRUCTURE AND STACKED CHIP PACKAGE AS WELL AS METHOD FOR MANUFACTURING CHIP STRUCTURES Public/Granted day:2009-09-17
Information query
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