Invention Grant
US07955917B2 Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
有权
使用镶嵌门法制造自对准砷化镓MOSFET
- Patent Title: Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
- Patent Title (中): 使用镶嵌门法制造自对准砷化镓MOSFET
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Application No.: US12233208Application Date: 2008-09-18
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Publication No.: US07955917B2Publication Date: 2011-06-07
- Inventor: Hussein I. Hanafi
- Applicant: Hussein I. Hanafi
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/338
- IPC: H01L21/338

Abstract:
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.
Public/Granted literature
- US20090011563A1 Fabrication of Self-Aligned Gallium Arsenide Mosfets Using Damascene Gate Methods Public/Granted day:2009-01-08
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