Invention Grant
- Patent Title: Full silicide gate for CMOS
- Patent Title (中): 全硅化物门CMOS
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Application No.: US11853284Application Date: 2007-09-11
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Publication No.: US07955921B2Publication Date: 2011-06-07
- Inventor: Huilong Zhu
- Applicant: Huilong Zhu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Daryl K. Neff; H. Daniel Schnurmann
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overlie edges of gates, source regions and drain regions of the PFET and NFET. Sputter etching can be used to remove a portion of the protective hard mask layer to expose the gates of the PFET and NFET. The semiconductor elements can be etched selectively with respect to the protective hard mask layer to reduce a thickness of the semiconductor elements. A metal may then be deposited and caused to react with the reduced thickness semiconductor element to form silicide elements of the gates.
Public/Granted literature
- US20090065872A1 FULL SILICIDE GATE FOR CMOS Public/Granted day:2009-03-12
Information query
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