Invention Grant
- Patent Title: Method of forming isolation structure for semiconductor integrated circuit substrate
- Patent Title (中): 形成半导体集成电路基板隔离结构的方法
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Application No.: US12150609Application Date: 2008-04-30
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Publication No.: US07955947B2Publication Date: 2011-06-07
- Inventor: Richard K. Williams
- Applicant: Richard K. Williams
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Analogic Technologies, Inc.
- Current Assignee: Advanced Analogic Technologies, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patentability Associates
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
Public/Granted literature
- US20080254592A1 Method of forming isolation structure for semiconductor integrated circuit substrate Public/Granted day:2008-10-16
Information query
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