Invention Grant
- Patent Title: Pseudo hybrid structure for low K interconnect integration
- Patent Title (中): 用于低K互连集成的伪混合结构
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Application No.: US12399372Application Date: 2009-03-06
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Publication No.: US07955968B2Publication Date: 2011-06-07
- Inventor: Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
- Applicant: Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Hamilton & Terrile, LLP
- Agent Michael Rocco Cannatti
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.
Public/Granted literature
- US20100227471A1 Pseudo Hybrid Structure for Low K Interconnect Integration Public/Granted day:2010-09-09
Information query
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